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Something similar to the above needs to be done for READs as well. Since each DRAM on the DIMM is located at a different distance, when a READ is issued each DRAM on the DIMM will see the READ command at different times and subsequently the data from each DRAM arrives at the ASIC/Processor at different times. During Initial Calibration, the ASIC/Processor figures out what the delays from each of the DRAMs are and trains its internal circuitry accordingly so that it latches the data from the various DRAMs at the right moment.
3014521210http://paper.people.com.cn/rmrb/pc/content/202603/14/content_30145212.htmlhttp://paper.people.com.cn/rmrb/pad/content/202603/14/content_30145212.html11921 中共中央办公厅国务院办公厅关于加快革命老区振兴发展的意见，更多细节参见谷歌
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